发明名称 Shared memory graphics accelerator system
摘要 A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-ship frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.
申请公布号 US6081279(A) 申请公布日期 2000.06.27
申请号 US19970955105 申请日期 1997.10.21
申请人 ALLIANCE SEMICONDUCTOR CORPORATION 发明人 REDDY, CHITRANJAN N.
分类号 G06T1/60;G09G5/36;G09G5/39;G09G5/397;G09G5/399;(IPC1-7):G06F15/76 主分类号 G06T1/60
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