发明名称
摘要 <p>A resetting method of a system enables an EEPROM writing to be implemented to the end normally, and it is capable of avoiding runaway of the whole system, even if reset signal is taken in caused by power failure while the EEPROM is of the writing state. In the system which has a CPU (10), an EEPROM whole circuit (11), an oscillation circuit (8), and a reset control circuit (14), when a system reset occurs, detecting a writing operation of the EEPROM cell (1), in cases where the EEPROM cell (1) is implementing the writing operation, holding the reset of the EEPROM cell (1) until the writing operation of the EEPROM cell (1) is terminated, thus implementing the reset of at least the CPU (10). <IMAGE></p>
申请公布号 JP3056131(B2) 申请公布日期 2000.06.26
申请号 JP19970168222 申请日期 1997.06.25
申请人 发明人
分类号 G11C16/02;G06F1/24;G11C16/22;(IPC1-7):G06F1/24 主分类号 G11C16/02
代理机构 代理人
主权项
地址