发明名称 VSB RECEIVER
摘要 PROBLEM TO BE SOLVED: To provide a VSB receiver with which high speed conversion in time required until a convergence processing end in an AGC circuit and a clock reproducing circuit is made to be compatible with high performance conversion in ghost interference removal and correct clock reproduction. SOLUTION: The loop gain of an AGC circuit and that of a clock reproducing circuit 6 are increased, until a synchronizing signal (a segment synchronizing signal or a field synchronizing signal) is detected (the gain of an amplifier is increased or the range of a loop filter is made wide). Then, the loop gain of the AGC circuit 7 and that of the clock reproducing circuit 6 are made to be small (the gain of the amplifier is reduced or the band of the loop filter narrowed).
申请公布号 JP2000174829(A) 申请公布日期 2000.06.23
申请号 JP19990269399 申请日期 1999.09.22
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KONISHI TAKAAKI;UEDA KAZUYA;AZAGAMI YASUSHI
分类号 H04N5/21;H04L7/08;H04L27/06;H04N5/44;H04N5/52 主分类号 H04N5/21
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