发明名称 MEMORY TESTING METHOD
摘要 PROBLEM TO BE SOLVED: To surely detect the short-circuit of the odd-numbered bits with each other and even-numbered bits with each other of a data bus and the disconnection and short-circuit of an address bus by writing the address value to a test object address and reading and collating the written value in addition to an FFFF test and a 0000 test. SOLUTION: This testing method is provided with the FFFF test for writing data whose bits are all 1 in the entire address area of a memory and then reading and collating the value, the 0000 test for writing the data whose bits are all 0 to the entire address area of the memory and then reading and collating the value and a unique data collation test for writing the data of an unique value in the address where the respective bits are 1 of the address bus of the memory and then reading and collating the value. In the testing method, a CPU 10 executes the program of the memory testing method. The CPU 10 is connected to the address bus 2, the data bus 3 and a control bus 16 and accesses respective devices through the buses 2, 3 and 16.
申请公布号 JP2000172569(A) 申请公布日期 2000.06.23
申请号 JP19980343478 申请日期 1998.12.02
申请人 NEC CORP 发明人 NAKADA TATSUHIRO
分类号 G11C29/34;G06F12/16;G11C29/00;(IPC1-7):G06F12/16 主分类号 G11C29/34
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