发明名称 VOLTAGE SIGNAL CONVERSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent the occurrence of error output in input voltage 0 V by giving reference voltage to input voltage in the former stage of a buffer and always applying the voltage of not less than a prescribed value to the buffer. SOLUTION: The dividing voltage point P3 of dividing voltage resistors Rc and Rd is connected to one end of a dividing voltage resistor Rb and a reference voltage part 2 is constituted. Reference voltage Vb is given to each end of the dividing voltage resistors Ra and Rb and input voltage Vin is converted in the former stage of a buffer 3. Even at the time of input voltage Vin=0 V, the conversion voltage Va of an input side in the buffer 3 becomes Va=0+Vb with reference voltage Vb. Since a 0 V signal is previously converted into the reference voltage Vb of the dividing voltage point P3 in the former stage of the buffer 3, 0 V is not applied to the buffer 3 and a voltage error owing to the application of voltage around 0 V does not occur. The output voltage Vout of the buffer 3 is not affected by the error.
申请公布号 JP2000163142(A) 申请公布日期 2000.06.16
申请号 JP19980333057 申请日期 1998.11.24
申请人 YAMATAKE CORP 发明人 TANAKA MITSURU
分类号 G05F1/56;H03H7/00;(IPC1-7):G05F1/56 主分类号 G05F1/56
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