| 摘要 |
<p>A cache device and a control method for controlling a cache memory of a multiprocessor system. A cache controller holds data which must be made ineffective for cache coherence as the data whose effectiveness is unclear, makes a cache-hit for a read request made by a processor, and provides the data as speculation data to process the data speculatively. Therefore, since the data, which must be fetched from the main memory of another cache because of the ineffectiveness, is held in an unclear state, a cache hit occurs, and hence the data waiting time of the processor is shortened.</p> |
