| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory device capable of expanding the capacity thereof as the merit of a buffered standard while being equipped with the high speed of operation as the merit of an unbuffered standard. SOLUTION: By inputting control signals RAS, CAS and WE to a buffer circuit 16c, the driving ability of SDRAM 161-164 can be held. Besides, a control signal CS is directly inputted to drive the respective SDRAM 161-164 in order to generate delay in the CS. Therefore, the falling and rising of this CS, which takes timing based on a CLK, can be formed within the width of about 2 nsec and about 1 nsec from the rising time of this CLK.
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