COMPUTER SYSTEM BUS ARCHITECTURE AND RELATED METHOD

摘要

A system and method for preventing address aliasing when using a single address cycle to transmit a target address in a computer system that includes target devices having addresses of different ranges. The computer system comprises a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range comprising a plurality of bits, and the second target device has a second address range comprising a fewer number of bits than the first address range. The initiator device transmits a signal indicating the size of the target address and also separately transmits in a single address cycle the target address. The second target device disables its address decode logic in response to the signal from the initiator device provided that the size of the target address is greater than the second address range. The second target device is thus prevented from responding to the target address, thereby preventing address aliasing.