| 摘要 |
An integrated circuit chip which is capable of avoiding a pad neck problem and capable of having a size suited for a circuit scale. The substrate 1 has circuit modules 6, 7 and 8 and input/output terminals 2 and 4 for inputting/outputting a signal to/from the circuit modules 6, 7 and 8. The input/output terminals 2 and 4 include terminals for operation time which input/output a signal during the operation time of the circuit modules 6, 7 and 8 and terminals for inspection which inspects the circuit modules 6, 7 and 8. The input/output terminals 2 are arranged on the substrate 1 along the edges of the substrate 1, and the input/output terminals 4 for inspection and the circuit modules 6, 7 and 8 are arranged on the substrate in an inner area than the input/output terminals for operation time. The input/output terminals 2 for operation are connected to leads 12 through bonding wires 14, while the input/output terminals 4 for inspection are not connected to the leads 12. <IMAGE> |
