发明名称 |
Logic circuit simulation apparatus having cycle-based simulator for simulating circuits including multi-cycle paths |
摘要 |
Where the output delay of a combinational circuit in a logic circuit is defined by a clock cycle count, data transfer means for outputting data delayed in the same number of clock cycles is inserted in a block of a cycle-based simulator. The data transfer means comprises registers or a combination of registers and selectors. The cycle-based simulator may be further arranged to automatically recognize the output delay of a combinational circuit in a target logic circuit. Data transfer means for effecting an output delay in the recognized number of clock cycles is then automatically inserted in a block of the cycle-based simulator.
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申请公布号 |
US6075936(A) |
申请公布日期 |
2000.06.13 |
申请号 |
US19980009930 |
申请日期 |
1998.01.21 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MORI, HIROYUKI;TANIGUCHI, MASAHIRO;INOUE, YOSHIO |
分类号 |
G01R31/28;G06F17/50;H01L21/82;(IPC1-7):G06F9/455 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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