发明名称 |
Method, architecture and circuit for half-rate clock and/or data recovery |
摘要 |
A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.
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申请公布号 |
US6075416(A) |
申请公布日期 |
2000.06.13 |
申请号 |
US19990283058 |
申请日期 |
1999.04.01 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
DALMIA, KAMAL |
分类号 |
H03L7/087;H03L7/089;H03L7/095;H03L7/14;H03L7/191;H04L7/033;(IPC1-7):H03L7/087;H03L7/099 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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