Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits

摘要

A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Artificially increasing the bit error rate of the chip reduces the amount of time required to test the chip to determine the acceptability of the chip and its actual bit error rate.