| 摘要 |
PROBLEM TO BE SOLVED: To minimize a coefficient of merit by forming a plurality of gate stripes by covering gate oxide stripes with conductive polysilicon stripes having a specified range of widths and spaces and overlying adjacent invertable channel regions and the space between respective base diffusions by the gate stripes. SOLUTION: A junction adhesion layer 52 is formed epitaxially on a substrate 51 and a field oxide layer is formed on the layer 52. Thereafter, the field oxide layer is selectively etched and stripes of a gate oxide layer 60 are formed. The gate oxide stripes 60 are covered with stripes of a conductive polysilicon layer 61 having a width in the range of about 3.2 to 3.5μm and a space in the range of about 1.0μm and a plurality of gate stripes are formed. The gate stripes overlie adjacent invertable channel regions 82 and the space between their respective base diffusions.
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