| 摘要 |
A bias circuit for a memory cell having first and second floating gate devices, and third and fourth reference devices, one of which has an output terminal coupled thereto is described. In one embodiment, the bias circuit includes a first capacitor including a first terminal coupled to the gates of the first and second devices, and a second terminal coupled to a power supply terminal, and a second capacitor including a first terminal coupled to the gates of the third and fourth devices, and a second terminal coupled to the power supply terminal. The bias circuit further includes a reference circuit including a first terminal having a first signal thereon and coupled to the gates of the first and second devices, and a second terminal having a second signal thereon and coupled to the gates of the third and fourth devices, the reference circuit to periodically turn on the first and second signals. The bias circuit reduces standby current and wake up time of redundant circuits in non-volatile memory devices.
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