| 摘要 |
PROBLEM TO BE SOLVED: To obtain an extremely reliable high integration where no latch-up is generated by covering all regions of lower and side surfaces with an insulation film for a bipolar transistor region, an n-type MOSFET region, and a P-type MOSFET region. SOLUTION: A thermal oxidation SiO2 film 12 is formed on an Si substrate and a single-crystal Si thin film 14 with an n+ diffusion layer 13 is formed on a lower surface. The element isolation region of the Si thin film 14 is formed by selectively eliminating Si and forming a groove and then burying the groove with an insulation film 15 up to the SiO2 film 12. Then, an n well 17 and a P well 16 are formed, and then a gate electrode 18, a collector n+ diffusion region 20, and a base P+ diffusion region 21 are formed. Then, after a source drain P+ diffusion layer 23 and n+ diffusion layer 22 are formed, a second-layer polycrystalline Si 25 and an emitter are formed before being covered with passivation SiO2 19 and 24. |
