发明名称 |
SEMICONDUCTOR MEMORY |
摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory where an operation is surely guaranteed and power consumption is reduced. SOLUTION: An external command latch circuit 23 latches an external command COM from an external command input buffer 22 in synchronism with a clock signal CLKZ. A command decoder 24 decodes the command COM which is latched by the circuit 23. A data input buffer 11 receives write data DQ and outputs the data DQ to first and second data latch circuits 13 and 14. A data strobe signal input buffer 12 outputs a data strobe signal DQS to the circuits 13 and 14 as a latch signal. A write command discriminating circuit 26 generates a first enable signal DSZ to active data input and clock signal input buffers 11 and 12 when the command COM inputted from the buffer 22 is a write command.
|
申请公布号 |
JP2000156082(A) |
申请公布日期 |
2000.06.06 |
申请号 |
JP19980327916 |
申请日期 |
1998.11.18 |
申请人 |
FUJITSU LTD |
发明人 |
TOMITA HIROYOSHI;KANDA TATSUYA |
分类号 |
G11C11/413;G11C7/10;G11C11/407;G11C11/409;G11C11/4096;(IPC1-7):G11C11/407 |
主分类号 |
G11C11/413 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|