| 摘要 |
<p>If a processor 10 is operating in a 'full-power' mode, a load/store unit 28, executing a load instruction directed to floating-point registers 36, loads 64 bits of data from a data cache 16 into a rename buffer 38 during a single processor cycle. If, however, the processor is operating in a 'special' power mode, then the 64 bits are loaded over two cycles instead (i.e. 32 bits per cycle), halving the number of sense amplifiers active at a time in the cache and so saving power. The maximum number of instructions fetched per cycle from an instruction cache 14, decoded and dispatched to execution units 20, 22, 26, 28, and the number of cache ways active at a time, may also be halved in the 'special' power-saving mode.</p> |
