| 摘要 |
<p>PROBLEM TO BE SOLVED: To make conflicts of access to a common memory decrease by themselves and to shorten the wait time of common bus access by allowing processors to communicate the values of common memory use levels of tasks being executed with each other as common memory level data including frequency information on access to the common memory. SOLUTION: Processor elements having processors 2 and 4 and memories 1 and 3 are present on local buses 5 and 6 and connected to the common memory 10 through bus bridges 7 and 8. This system has a function of arbitrating against access from the processor elements to the common memory 10 and is equipped with a signal line for transferring the common memory use level data between the processor elements and task schedulers 12 and 13 which can select program tasks to be run on the processors according to the state of the signal line. The common memory use level data are thus transferred between the processors 2 and 4 to reduce access to the common memory 10.</p> |
