发明名称 TEST HANDLER SYSTEM AND CONTROL METHOD FOR THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a test handler system, together with a control method for it, having small occupancy space and high throughput. SOLUTION: A test part 4 for testing the electrical characteristics of an IC 10 which is to be tested, a loader part 2 for supplying the IC 10 to the test part 4, an unloader part 5 where a semiconductor device tested by the test part 4 is housed, and a memory 15 are provided. Here, based on a test result by the test part 4, an IC classifying part 32 classifies each of the ICs 10 into a sound or defective article as well as into categories of grades corresponding to their level, and an IC transfer part 9, in accordance with the classification result, houses the ICs 10 in a sound article housing place 26 or a defective article housing place 27 in a prescribed order. The classification result of IC are housed in a test result management table 16 of the memory 15 according to the housing place at the unloader part 5 and that specified by the housing order of the IC 10.
申请公布号 JP2000147056(A) 申请公布日期 2000.05.26
申请号 JP19980326521 申请日期 1998.11.17
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 AKAGI YASUO
分类号 G01R31/26;H01L21/66;(IPC1-7):G01R31/26 主分类号 G01R31/26
代理机构 代理人
主权项
地址