发明名称 Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library
摘要 In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and the thickness of a gate oxide film based on said specified operating power-source voltage data. Thereafter, a ratio of a drain saturation current in the P-channel MOSFET when a reference power-source voltage is applied thereto to the drain saturation current in the P-channel MOSFET when an operating power-source voltage is applied thereto, thereby determining a delay power-source coefficient. Next, in an effective-delay calculating step, effective-delay calculating means multiplies a delay time when the reference power-source voltage calculated by the delay calculating means is applied thereto by the delay power-source coefficient calculated by delay-power-source-coefficient determining means to determine a delay time at the operating power-source voltage.
申请公布号 US6066177(A) 申请公布日期 2000.05.23
申请号 US19970917210 申请日期 1997.08.25
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 HATSUDA, TSUGUYASU
分类号 H01L29/00;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 H01L29/00
代理机构 代理人
主权项
地址
您可能感兴趣的专利