发明名称 Method and data processor for synchronizing multiple masters using multi-bit synchronization indicators
摘要 A method and apparatus for syncing multiple bus masters (110, 120, 130, 140) utilize a sync bus (160) to communicate synchronization information between a plurality of bus masters. For each bus master, a check is made after instruction fetch (350) for a "sync indicator" (360). When a sync indicator is detected (360), the bus master transmits sync signals on the sync bus (160) indicating which masters it needs to sync with (365). The bus master then stalls instruction dispatch (390) until the corresponding sync signals are received (370) on the sync bus (160) from the other bus masters. A further programmed delay may be introduced after the bus masters have matched sync signals (375), enabling through testing for timing windows.
申请公布号 US6067610(A) 申请公布日期 2000.05.23
申请号 US19960688633 申请日期 1996.07.29
申请人 MOTOROLA, INC. 发明人 WILSON, GLEN E.
分类号 G06F9/00;(IPC1-7):G06F9/00 主分类号 G06F9/00
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