发明名称 Multilevel interconnection forming method for forming a semiconductor device
摘要 The multilevel interconnection forming method of the present invention comprises the following. A metal film containing aluminum is deposited on an insulating film of a substrate, and the metal film is patterned, to form a wiring layer of a first layer. An interlayer dielectric film forming part of the first layer is formed on an entire surface of the substrate, such that the interlayer dielectric film covers the wiring layer from upside. A hole is formed at a predetermined position of the interlayer dielectric film such that the hole reaches the wiring layer of the first layer. Aluminum is selectively deposited and filled into the hole by a CVD method, such that the aluminum is filled at a volume ratio smaller than 100% with respect to the hole. An active metal film is formed on an entire upper surface of an interlayer dielectric film including the hole filled with the aluminum. A metal layer containing aluminum is formed on the active metal film. The metal layer is made to flow into the hole by reflowing, to completely fill the hole and to planarize the surface of the metal layer. The metal layer is subjected to be patterned, to form a wiring layer of a second layer, after the surface of the metal layer is planarized by the reflowing.
申请公布号 US6066558(A) 申请公布日期 2000.05.23
申请号 US19970796695 申请日期 1997.03.04
申请人 TOKYO ELECTRON LIMITED 发明人 KAWANO, YUMIKO;HOSAKA, SHIGETOSHI;WADA, YUICHI;KOBAYASHI, HIROSHI;YANO, TETSUYA
分类号 H01L21/285;H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/285
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