| 摘要 |
PROBLEM TO BE SOLVED: To accurately control the characteristics, e.g. saturation drain current and pinch-off voltage by forming an embedded layer, such that it is located on the interface of a semiconductor substrate and an epitaxial layer through high energy ion implantation, thereby determining the channel thickness uniquely. SOLUTION: An N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1 and a P-type insulating diffused layer 3 is made through the N-type epitaxial layer 2. Boron ions are then implanted at high energy over the entire surface of a wafer. A boron ion implanted layer, i.e., an embedded boron layer 8, serving as a back gate is formed across the interface of the P-type semiconductor substrate 1 and the N-type epitaxial layer 2. Subsequently, boron ions are implanted selectively from the surface of the N-type epitaxial layer 2 to form a P-type top gate diffused layer 4. Finally, an N+-type source diffused layer 6 and an N+-type drain diffused layer 7 are formed to complete an N- channel JFET. According to the structure, saturation drain current IDSS and pinch-off voltage VP of the JFET can be controlled easily.
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