| 摘要 |
PROBLEM TO BE SOLVED: To improve reliability and productivity of a multilayer interconnection by providing a wiring structure, together with its manufacturing method, where an oxidation-resistant metal is selectively formed on at least a surface of a pad region of a chip, when a copper is embedded in a wiring groove at a top layer of an LSI. SOLUTION: A second metal forming an inert oxide is embedded on the surface of a first metal through a series processes comprising a process, where at least a bonding pad groove 35 is formed at a top layer insulating film 34, a process where a first metal 36 which is thinner than the depth of the bonding pad groove is formed, a process where a second metal forming an inert oxide is formed on the first metal, and a process where the first and second metals on the surface of the top layer insulating film are removed. For a multilayer interconnection top layer comprising a wiring region and a bonding pad region, a second metal forming an inert oxide layer is formed on the surface of the first metal which is embedded in an interlayer insulating film of the top layer. |
