FRAME BUFFER CONTROL DEVICE IN A D-RAM INTERFACE OF PDP TELEVISION

摘要

PURPOSE: A frame buffer controller in a dynamic RAM interface apparatus of a PDP television is provided to normally record and read data by setting an access time and a cycle time using a line buffer in the front of a DRAM. CONSTITUTION: A frame buffer unit(100) receives an NTSC composite video signal, and temporarily stores an R/G/B color signal digitalized and outputted. A PISO unit(110) rearrays data in serial. A memory unit(120) is composed of the first DRAM(120a) and the second DRAM(120b) which store the R/G/B data outputted from the PISO unit(110). A data selection unit(130) reads data relevant to an address applied from a DRAM address generation unit(150), and outputs the data. A PDP(140) displays the R/G/B data outputted from the data selection unit(130). A line buffer control unit(170) is connected to the frame buffer unit(100), and controls the buffer(100). A load clock and shift pulse generator(160) generates a load clock and a shift pulse. A DRAM address generation unit(150) provides an address needed to the memory unit(120).