| 摘要 |
PROBLEM TO BE SOLVED: To realize inexpensively a variable delay circuit from which a desired delay is obtained without being affected by a power supply voltage or the like. SOLUTION: The variable delay circuit is provided with a 3-bit counter 10 that generates data pulses TP, TP2, TP4 with a prescribed period based on a received clock, an up-down counter 20 that counts based on an up-down control signal UD, a delay line 30 whose delay number is set with a count output of the up-down counter 20, a delay amount detection section 40 that detects the delay by the delay line 30 and outputs the result of detect as the up-down control signal UD, and a delay lock detection section 50 that compares a current count output of the up-down counter 20 with a preceding count output to detect whether or not the delay is locked and provides an output of a required count in the two counts as a reference delay stage number. However, a period of the data pulses is selected as TP<TP2<TP4.
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