| 摘要 |
PROBLEM TO BE SOLVED: To actualize lower power consumption and high integration by greatly decreasing the number of parity check circuits which check the parity of address data. SOLUTION: To a parity check circuit 5 provided to a cache memory 1, address data to be accessed is inputted directly and the parity is checked. Consequently, the need to check the parity of address data read out of respective memory blocks 41 to 416 of an address cache RAM 4 is eliminated to greatly decrease circuits which check the parity.
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