| 摘要 |
<p>The bistable circuit comprises a master unit (M) receiving an input variable (D) and producing first intermediate variables (M,NM). A transfer unit (T) contains two logic gates (3,4) with a clock signal connection (CK). This produces second intermediate variables (X,Y) as functions of the input variable and the clock signal, which are fed back to the master unit. A slave unit (E) produces at least one output variable (Q,NQ). One input of logic gate (3) is connected directly to receive the intermediate variable (M), and one input of logic gate (4) is connected via an inverter (5) to receive a complement (I) of the variable (M). The intermediate variables (X,Y) are mutually independent. In the preferred embodiment, each unit, master, transfer, and slave (M,T,E), contains two NAND gates. In the second embodiment the slave unit contains a NAND and a NOR gates, and two additional inverters. In the third embodiment the master unit contains a NAND and a NOR gates, and an additional inverter in one feedback loop. In the fourth embodiment the master unit is as in the third embodiment, and the slave unit as in the second embodiment. In the fifth embodiment the transfer unit contains an additional NOR gate connected to a control input (CN) via an inverter for set or reset. In the sixth embodiment the master and the slave units are with control inputs (CN). In the seventh embodiment the units are as in the preferred embodiment, but all with NOR gates. In the eighth embodiment the balanced circuit is connected for use as a divisor by two circuit, where the intermediate signals (X,Y) are in counter phase with frequency equal to half that of the clock signal.</p> |
