| 摘要 |
PCT No. PCT/JP97/04720 Sec. 371 Date Aug. 13, 1998 Sec. 102(e) Date Aug. 13, 1998 PCT Filed Dec. 19, 1997 PCT Pub. No. WO98/27556 PCT Pub. Date Jun. 25, 1998In a memory testing apparatus capable of testing both memories of a parallel input/parallel output type and a serial input/serial output type, in case of testing the serial input/serial output type memory, failure data in read out data serially outputted from the memory are separated in bit by bit basis and are stored in a failure analysis memory at different time points in the time axis so that a failure bit position can be specified. A failure multiplexer 14 for selecting and taking out outputs from a terminal of a memory under test 10 is provided in the output side of a logical comparator 13, and a bit selector 17 is provided between the failure multiplexer and a failure analysis memory 15. When a memory under test of serial input/serial output type is tested, a serial failure data outputted from the failure multiplexer is separated by the bit selector in bit by bit basis and are supplied to the failure analysis memory at different time points in the time axis, thereby to store failure bit positions in the failure analysis memory.
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