发明名称 |
ATM cell receiver system with source clock recovery |
摘要 |
A cell disassemble circuit in a cell receiver system detects the number of lost cells from information for detecting cell loss included in received cells, and separates a payload from a header in each of the received cells. The number of lost cells indicates the number of cells lost on a transmission path from the transmission side to the cell receiver system. A buffer stores the number of detected lost cells and data inserted in the payloads. A phase locked loop recovers a source clock corresponding to the rate of fixed rate information based on a use level of the buffer. A counter circuit generates a clock for reading data from the first buffer from the recovered source clock. Also, the counter circuit stops outputting the read clock to the buffer for a time period corresponding to the number of lost cells.
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申请公布号 |
US6061352(A) |
申请公布日期 |
2000.05.09 |
申请号 |
US19960759879 |
申请日期 |
1996.12.03 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;KOKUSAI DENSHIN DENWA CO., LTD. |
发明人 |
YAMAZAKI, KATSUYUKI;YAGI, SHINOBU;FUKUI, AKITO |
分类号 |
H04L7/033;H04L7/08;H04L12/56;H04Q3/00;H04Q11/04;(IPC1-7):H04L12/38;H04J3/06 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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