发明名称 |
Programming utility register to generate addresses in algorithmic pattern generator |
摘要 |
A algorithmic pattern generator (APG) in a memory tester having a programmable first ALU generating an first value on a first output data path; a programmable Z ALU generating a Z value on an Z output data path; and a programmable second ALU having terminals to receive the Z value from the Z ALU and a circuit to insert bits of the received Z value into low order bits of a second value before outputting the second value on a second output data path. In embodiments, the first value and the second value are generated to define a location in an array of memory cells of a memory under test; and the second value contains low order bits corresponding to address bits that are incremented internally by the memory under test in a burst mode of operation. Also, a method of programming a memory tester APG to test a memory device including providing to the APG for execution a single instruction setting a value representing a non-zero burst length n and a value representing a non-zero seed for generating interleaved addresses. In embodiments, the method includes providing an increment instruction to a counter n times for execution by the APG without an intervening instruction to reset the counter; and using the n values of the counter from the preceding step to form n addresses to test the memory device in a burst mode of operation with an interleaved addressing mode.
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申请公布号 |
US6061815(A) |
申请公布日期 |
2000.05.09 |
申请号 |
US19960762611 |
申请日期 |
1996.12.09 |
申请人 |
SCHLUMBERGER TECHNOLOGIES, INC. |
发明人 |
SOBELMAN, MICHAEL J. |
分类号 |
G01R31/28;G01R31/3181;G01R31/3183;G11C29/10;G11C29/36;G11C29/56;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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