| 摘要 |
Integrated circuit memory devices having time compensated column selection capability include a column selection signal controller which performs the functions of generating: a control signal during read and write modes of operation, a read column selection enable signal based on the control signal during the read mode of operation and a write column selection enable signal based on a delayed version of the control signal during the write mode of operation, in response to a clock signal. Using this controller, the delay between generation of the control signal and the write column selection enable signal is greater than the delay between generation of the control signal and the read column selection enable signal. This greater delay provides a greater data access time (e.g., setup time) during write operations and thereby improves the reliability of these write operations by enabling data lines to become sufficiently charged and enabling sufficient time for data transfer between input/output lines and bit lines of a memory cell array, such as a DRAM array. A column selection circuit is also provided and this decoder is responsive to a column address and the read and write column selection enable signals. The memory cell array is electrically coupled by a sense amplifier to the column decoder.
|
