发明名称 |
CMOS preferred state power-up latch |
摘要 |
A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.
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申请公布号 |
US6060919(A) |
申请公布日期 |
2000.05.09 |
申请号 |
US19980205033 |
申请日期 |
1998.12.04 |
申请人 |
RAMTRON INTERNATIONAL CORPORATION |
发明人 |
WILSON, DENNIS R.;KRAUS, WILLIAM F. |
分类号 |
H03K3/356;(IPC1-7):H03K3/37 |
主分类号 |
H03K3/356 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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