发明名称 Format sensitive timing calibration for an integrated circuit tester
摘要 Each channel of an integrated circuit tester includes at least one timing signal generator for producing an output timing signal for triggering various types of test events carried out by the tester channel. At the start of each cycle of a test, each timing signal generator receivies input timing data referencing a time at which a test event is to occur and also receives input format data indicating the format of that test event. Each timing signal generator then generates its output timing signal before the event time referenced by the timing data with a lead time selected by the input format data. Each timing signal generator may be independently calibrated such that the format data always selects the appropriate lead time for the event to be triggered so that each type of event occurs at the time indicated by the input timing data regardless of the nature of the event being triggered.
申请公布号 US6060898(A) 申请公布日期 2000.05.09
申请号 US19970941452 申请日期 1997.09.30
申请人 CREDENCE SYSTEMS CORPORATION 发明人 ARKIN, BRIAN J.
分类号 G01R31/28;G01R31/3183;G01R31/319;(IPC1-7):G01R31/26 主分类号 G01R31/28
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