发明名称 Method and apparatus for vertical congestion removal
摘要 Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. To reduce vertical congestion, the cells are moved from congested regions to uncongested regions. The present invention discloses techniques of defining regions as pieces and columns, determining the level of congestion in the regions, and the methods of moving the cells to different columns to reduce congestion while minimizing affects to wire routing. The movement of the cells to other columns may create overlapping of the cells or overloading of the columns. The present invention also discloses the methods to resolve the overlapping and overloading problems.
申请公布号 US6058254(A) 申请公布日期 2000.05.02
申请号 US19970906948 申请日期 1997.08.06
申请人 LSI LOGIC CORPORATION 发明人 SCEPANOVIC, RANKO;ANDREEV, ALEXANDER E.;PAVISIC, IVAN
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址