METHOD FOR PERFORMING ATOMIC UPDATE PROCESS

摘要

PROBLEM TO BE SOLVED: To perform the fastest update process on the hardware of a computer by performing the atomic update process by using a cache coherency mechanism when an instruction which can be exported can not be supported at a memory position accessed by the atomic update process. SOLUTION: An entry 38 of a conversion index buffer (TLB) 36 includes a memory access bit field 44. Then it is judged whether or not the instruction which can be exported is supported at the memory position access through the atomic update process by accessing this field 33. When the instruction which can be exported is supported, the atomic update process is exported to a center location. When the instruction is not supported, on the other hand, the cache coherency mechanism is used to perform the atomic update process.