| 摘要 |
In a processor separate register file memories (33, 35) are arranged in a pipelined manner. The processor executes jobs having different priorities using for each job a register file stored in a register file memory assigned to the priority of the job. During the execution of the job data corresponding to a successive job of the same priority, the data of which for example is arranged ina queue (9), are stored in a standby register file memory (35). When finishing the ongoing job, the successive job having the same priority can start to be executed much faster since no or very little time is required for changing the contents of the register file memory. Instead, all that needs to be performed is to switch (37) to the standby register file memory to make it be connected to the Arithmetic Logic Unit ALU (27) of the processor. The previously active register file memory (33) will then be the standby one, and can receive a new register file for the same priority or a different priority when said successive job is executed. The processor is particularly useful for application in which jobs are frequently changed, such as a processor connected to a telephone exchange.
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