| 摘要 |
FIELD: computer engineering, in particular, digital signal processing, mathematical physics, computers with pipe flow architecture, and multiprocessor computers. SUBSTANCE: speed of processing n-bit numbers represented in quaternary notation by device is equal to n/2. Device represents numbers using binary redundant notation. Precision of calculations for non-normalized numbers is equal to n/2 + 2. Device has combination adder 14, first multiple register 12, partial product register 15. Goal of invention is achieved by introduced input unit 3, power unit 5, output digits former 6, output register 7, two multipliers 13 and 16, second multiple register 17, clock pulse distributor 18. EFFECT: prevention of false overflow of result power, increased functional capabilities due to correct standard output of result. 2 cl, 8 dwg, 1 tbl
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