| 摘要 |
<p>PURPOSE: A semiconductor integrated circuit device is provided to prevent an overflow and an undeflow generated when a frequency of an external clock signal is higher and when the frequency thereof is lower, respectively, and to have an immunity against a power noise without increasing a chip area. CONSTITUTION: In a semiconductor integrated circuit device, an one-half divider(30) divides an input clock signal with an one-half division rate. A selector circuit(32) selects either one of the input clock signal and an output signal from the one-half divider according to a frequency of the input clock signal. A DLL circuit(35) controls the delay amount of a variable delay circuit in order to synchronize a phase of a reference clock and a phase of a dummy clock. The reference clock is generated to divide the input clock signal, and the dummy clock is obtained by delaying a divided input clock signal via the variable delay circuit and a dummy circuit(46).</p> |
