发明名称 ARITHMETIC CIRCUIT ON FINITE FIELD
摘要 PROBLEM TO BE SOLVED: To provide an economical arithmetic circuit capable of further reducing the storage capacity of a conversion table by providing a second switch part or the like for switching the conversion table and the output value of an adding part respectively composed of (m) bits corresponding to the most significant bit(MSB) of an input register and outputting the result as a specified value. SOLUTION: Concerning this arithmetic circuit on a finite field, whenαon an m-th order extension field GF(2m) provided by an n-th order irreducible polynomial P(x) on a finite field GF(2) is defined as the source element of the extension field GF(2m) and the -∞power of this source elementαis defined as '0', K of sumαk ofα0=1 andαn is found. When the MSB of an input register 1 is '1', a second switch part 6 selects the output of an adding part 5 and when it is '0', the value read out of the conversion table 4 is selected and defined as an output signal (k). In this case, the conversion table 4 can use a Zech logarithm prepared in the relation of n<(2m-1)/2, the storage capacity of m×2m-1 is made enough and the storage capacity can be reduced by half.
申请公布号 JP2000112926(A) 申请公布日期 2000.04.21
申请号 JP19980280789 申请日期 1998.10.02
申请人 FUJITSU LTD 发明人 NAKAMURA TAKAHARU;KAWABATA KAZUO;OBUCHI KAZUCHIKA
分类号 G06F11/10;G06F17/10;G09C1/00;H03M13/00;(IPC1-7):G06F17/10 主分类号 G06F11/10
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