发明名称 NONVOLATILE MEMORY AND ITS ERASURE METHOD
摘要 PROBLEM TO BE SOLVED: To provide a nonvolatile memory whose erasure efficiency is not lowered and which can restrain a current which flows when a source line is charged. SOLUTION: A floating gate and a control gate are provided at this nonvolatile memory. In the nonvolatile memory, a high voltage is applied to a source, and data inside a memory is erased, A first power supply P2 which is installed so as to charge a source line SL connected to sources of nonvolatile memories MC1 to MC4 and whose current supply capability is low is constituted. In addition, a second power supply P1 whose current supply capability is higher than that of the first power supply P2 is constituted. In addition, a control means DLY which controls the operation of the first power supply P2 and the operation of the second power supply P1 is constituted.
申请公布号 JP2000113692(A) 申请公布日期 2000.04.21
申请号 JP19980285033 申请日期 1998.10.07
申请人 NEC KYUSHU LTD 发明人 SANO YUICHI
分类号 G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/06;H01L21/824 主分类号 G11C16/06
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