| 摘要 |
An input pulse signal is applied to an input terminal of a pulse width controlling logic circuit and integrated by an integrating circuit. A desired output signal is obtained at an output terminal via a C-MOS logic element having an input threshold level that depends on a power supply voltage applied thereto, and an ACC circuit. An average level detecting unit detects an average level of the input pulse signal so that an average level converting unit supplied with an output from the average level detecting unit controls the power supply voltage applied to the C-MOS logic element. The pulse width controlling logic circuit operates on a principle that, as a pulse width is decreased, an average level of the pulse is lowered, and, as a pulse width is increased, an average level of the pulse is raised. Since an input threshold level of a C-MOS logic element depends on the power supply voltage applied thereto such that the threshold level is +E,fra 1/2+EE the level of the power supply voltage. By controlling the power supply voltage, the threshold level is lowered or raised so that the pulse width is increased or decreased. Accordingly, the circuit outputs a signal having a desired pulse width.
|
