8X8 BLOCK ADDRESS GENERATING CIRCUIT FOR JPEG CODING

摘要

PURPOSE: An 8x8 block address generating circuit of a JPEG image compression is provided to economize the cost, to improve a data transmission speed, and to reduce a system size by transmitting an image data stored in a frame memory to an image compression chip. CONSTITUTION: A 13 bit horizontal counter(21) receives an A/D sampling clock and provides a horizontal address in units of the 8x8 block in order to read only valid data in a frame memory having a size of 1024x512. A 6 bit vertical counter(22) provides a vertical address in units of 8x8 block. A 2 input AND gate(G1) receives outputs(H11,H12) of 13 bit horizontal counter(21) and provides a clock signal of the 6 bit vertical counter(22) and a clear signal of 13 bit horizontal counter(21). A 4 input AND gate(G2) receives outputs(V2,V3,V4,V5) of the 6 bit vertical counter(22) and provides a clear signal of the 6 bit vertical counter(22).