| 摘要 |
PURPOSE: A test pattern of a semiconductor device is provided to reduce the area of the test pattern and to test easily by forming the first metal layer and a source as one pad to reduce the number of the pad in the test pattern of the semiconductor device. CONSTITUTION: A p-well is formed on a n-type semiconductor substrate, and a plurality of active regions and a plurality of field regions isolating the active regions is defined and a field oxide film formed thereon. A polysilicon(24) is formed on the upper side and the lateral sides on the field oxide film in a certain direction at a regular interval. The first metal layer(25) is formed to contact the upper side of the polysilicon(24) in the same direction at a regular interval. The width of the first metal layer(25) is wider than that of the polysilicon(24). A source/drain impurity diffusion region(26, 27) is formed on the active regions of the semiconductor substrate. The second metal layer(28) is formed over the upper sides of the polysilicon(24) and the first metal layer(25), and a p-type bulk region(29) is formed on the outside of the active regions. The first pad(30a) contacts both of the source impurity diffusion region(26) and the first metal layer(25), the second pad contacts the drain impurity diffusion region(26), the third pad contacts the second metal layer(28), and the fourth pad(31d) contacts the bulk region(29).
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