| 摘要 |
<p>An ADRC encoder generates, regarding an ADRC block of 4x4 pixels, DR, MIN and quantized data corresponding to each pixel. A macro block formatting circuit generates code data DR, MIN and DT of four ADRC blocks. An adding circuit generates sum data (DR =DR1 + DR2 + DR3 + DR4, same calculation regarding MIN) of important data in the macro block. Mixing circuits insert the sum data into recording data as additional data. The sum data and the important data are distributed and recorded in plural channels. If one of the important data has an error and the remaining important data and the sum data have no error, the important data with the error can be completely corrected. Error correction of the important data and the quantized data generated by block encoding is effected with restrained increase in redundancy. Input data which has been reproduced and DCT-decoded is supplied to and is converted into 3x3 block format by a 3-line memory and block formatting circuit . An ADRC encoding circuit generates encoded data DTx of a center pixel data and data DT which is made up of peripheral 8 pixel data. A timing aligning circuit generates class information comprising 8 pixel data and the class information is supplied to a memory as a read address. Memory stores existing-range data and predicted data DTx^ through in-advance training. An error is detected by comparing the existing-range data and reproduced data DTx and when there is an error, predicted data DTx is selected. Error correction of received or reproduced image data is effected without using an error correction code. <IMAGE> <IMAGE></p> |
