| 摘要 |
Semiconductor memory or store layout arrangement includes a number of memory cells (SZ1,SZ2) and at least one selection transistor (AT1,AT2) is used with at least one capacitive element (ST) in each of the memory or storage cells (SZ1,SZ2), with the load paths connected in series. The series arrangement of the load paths defines an output of a memory cell (SZ1,SZ2) which is connected via two contact terminals (K1,K2) to two output lines (BL1,BL2), The output paths (A1,A2) of each adjacent memory or storage cell are connected to a common output line (BL1,BL2). The output path (A1;A2) of a memory cell (SZ1,SZ2) is made specifically L-shaped, in the lateral projection. The capacitive element (KE) is specifically designed as a storage transistor (ST1,ST2) or as a storage capacitor.
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