| 摘要 |
A Triple Modular Redundancy (TMR) unit 10 comprises a plurality of processors 10-1 to 10-n connected by a bus 12 and simultaneously executing the same processing operation. Among the processors, one of them, 10-1, is a master and the remaining processors, 10-2 to 10-n, are slaves. Information formed only by the master processor is outputted to the bus. Each processor has a multiplex control circuit 48 which compares the output information formed by the respective processor with the information outputted to the bus, thereby detecting a failure and allowing an internal circuit 46 to execute, necessary processes. Described embodiments relate to the timing of the output of the comparison results; providing means in each processor to indicate which of the processors are normal and which have been disconnected; providing bus failure detecting circuits; using a memory control unit to allow slave processors to access the master processor memory via the bus when exchanging a failed processor; using a directory memory to validate directory information so as to indicate the newest information in a memory when a processor is exchanged.
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