| 摘要 |
A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps: Firstly, a pad oxide layer and a n+ (such as phosphorus) doped oxide layer is successively formed on the silicon substrate. Then, a nitride layer is deposited on all surfaces as an antireflection coating layer. After coating a patterned mask on the nitride layer to define a plurality of buried bit line regions, a dry etch is used to etch the unmask region till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and an oxidation process to grow an oxynitride layer on resultant surface and form buried bit line using dopants in the oxide layer as a diffusion source. After refilling a plurality of trenches with n+ doped silicon layer, a planarization process such as CMP is done to form a plain surface using the nitride layer as an etching stopped layer. A stacked ONO layer is then deposited as an interpoly dielectric layer; Finally, another n+ doped polysilicon layer is formed and patterned to be word lines.
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