| 摘要 |
The invention relates to an RS flip-flop and to an RS flip-flop provided with a clock input, and to a frequency divider to be implemented therewith. To produce for example a fast divider generating a clock signal with a symmetrical pulse ratio, a frequency divider is constructed from two RS flip-flops provided with a clock input by means of a master-slave connection. In such a case, both the master and the slave flip-flop include and RS flip-flop (RS_FF) having two cross-connected inverters (1' and 2') known per se and two control means (M3' and M6') for forced control of the inverters through setting and resetting inputs to the desired state. Furthermore, a third and fourth inverter (1 and 2) are connected ahead of the RS flip-flop (RS_FF), so that the input of each inverter constitutes a clock input (CLK). The output of the third inverter is connected to the setting input of the flip-flop (RS_FF), and the voltage supply terminal (P1) of the inverter constitutes a second setting input (SET) for activating the inverter to input the desired clock signal by means of the set signal to the setting input of the flip-flop (RS_FF). The output of the fourth inverter is connected to the resetting input of the flip-flop (RS_FF) and the voltage supply terminal (P2) of the inverter constitutes a second resetting input (RESET) for activating the inverter to input the desired clock signal by means of the reset signal to the resetting input of the flip-flop (RS_FF). |
