CLOCK GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To make generable phase matched internal clocks from respective clock phase control circuits irrespective of distances from the clock input terminal of a clock generating circuit to the respective clock phase control circuits. SOLUTION: In respective clock phase control circuits 100A and 100B connected to clock wiring 100, outgoing and incoming clocks propagated on the clock wiring are received and by comparing the phase of an outgoing clock CKg delayed by each circuit with that of an incoming clock CKr from the clock wiring, feedback control is performed to the phase of the outgoing clock CKg so that internal clocks CLKA and CLKB having the phase equal with the phase of a clock to pass the return point of the clock wiring can be generated.